India trains 67,000 people in chip design under Rs 250 crore Chips to Start-up programme

The Indian government has said that more than one lakh people have enrolled in chip design training under its Chips to Start-up or C2S Programme, with around 67,000 participants already trained so far.

The programme is aimed at building a strong domestic semiconductor design ecosystem and preparing skilled manpower for the growing global chip industry.

The C2S Programme was launched by the Ministry of Electronics and Information Technology in 2022 with a total outlay of Rs 250 crore for five years. It focuses on hands-on training in Very Large Scale Integration, embedded systems, and full chip design flow, from concept to fabrication and testing.

According to the government, the programme is being implemented across 305 academic institutions in the country. These include Indian Institutes of Technology, National Institutes of Technology, and several state and private universities. The training covers students at the BTech, MTech, and PhD levels, along with faculty members.

The government has set a target of creating around 85,000 industry-ready professionals. This includes 200 PhD scholars, about 15,800 MTech students across different specialisations, and nearly 69,000 BTech students with exposure to chip design and related technologies.

A key feature of the programme is its focus on practical experience. Students are given access to advanced electronic design automation tools, industry-standard workflows, and national infrastructure. They work on real design projects such as application-specific integrated circuits, systems on chip, and reusable IP cores.

The ChipIN Centre, operated by C-DAC in Bengaluru, plays a central role in the programme. It provides shared access to commercial design tools and supports institutions with training and technical guidance.

The centre has conducted more than 265 training sessions in collaboration with industry partners and handled thousands of technical support requests from students and researchers. For fabrication, student designs are sent for manufacturing through shared wafer runs at the Semiconductor Laboratory in Mohali using 180 nanometre technology.

So far, six shared wafer runs have been completed. A total of 122 design submissions were received from 46 institutions, resulting in 56 student-designed chips being fabricated, packaged, and delivered for testing and validation.

The government said that the programme has also led to strong research output. Participating institutions have filed more than 75 patents and are working on over 500 chip design projects and IP cores for use in sectors such as defence, telecom, automotive, industrial electronics, and consumer products. Officials said the initiative is important at a time when the global semiconductor industry is facing a shortage of skilled professionals.

The C2S Programme, along with other schemes such as the Design Linked Incentive, is expected to help India build long-term capability in chip design and reduce dependence on foreign technology.

The government said it will continue to expand training, research, and industry collaboration under the programme to position India as a key hub for semiconductor design and innovation in the coming years.